The present invention relates to manufacturing semiconductor devices, particularly to manufacturing gate dielectric layers for Replacement Gate Field Effect Transistor (FET) structures.
FETs are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. In planar FETs, the semiconductor channel region may be a semiconductor substrate. In finFETs, the semiconductor channel region may be a semiconductor fin. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
FinFETs are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 22 nm node. FinFET structures include at least one narrow semiconductor fin as the channel region of the FET and are gated on at least two sides of each of the at least one semiconductor fin. FinFETs including more than one fin may be referred to as multi-fin FinFETs. FinFETs may be formed on bulk substrates to reduce wafer cost and/or enable formation of certain devices in the bulk substrate.
Due in part to the relative instability of the dielectric layer and work function metal layer of the gate, a gate-last process, also known as a replacement metal gate process, may be used where a sacrificial gate is formed prior to forming other components of the FET. The sacrificial gate may then be removed to form a recessed region that may then be filled with a replacement metal gate potentially including a gate dielectric layer, a work function metal layer, and a metal electrode.